1. Field of the Invention
The present invention relates to crystalline substrate structures such as, for example, high-performance complementary metal oxide semiconductor (CMOS) circuits, in which carrier mobility is enhanced by utilizing different semiconductor surface orientations for p-channel field effect transistors (pFETs) and n-channel field effect transistors (nFETs). More particularly, the present invention relates to an improved amorphization/templated recrystallization technique for fabricating planar hybrid orientation substrate structures comprising semiconductors with different surface crystal orientations.
2. Background of the Invention
Semiconductor device technology is increasingly relying on specialty semiconductor substrates to improve the performance of the n-channel MOSFETs (nFETs) and p-channel MOSFETs (pFETs) in complementary metal oxide semiconductor (CMOS) circuits. For example, the strong dependence of carrier mobility on silicon orientation has led to increased interest in hybrid orientation Si substrates in which nFETs are formed in (100)-oriented Si (the orientation in which electron mobility is higher) and pFETs are formed in (110)-oriented Si (the orientation in which hole mobility is higher), as described by M. Yang, et al. in “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” IEDM 2003 Paper 18.7 and U.S. patent application Ser. No. 10/250,241, filed Jun. 17, 2003 entitled “High-performance CMOS SOI devices on hybrid crystal-oriented substrates.”
Amorphization/templated recrystallization (ATR) methods for fabricating hybrid orientation substrates such as disclosed, for example, in U.S. patent application Ser. No. 10/725,850, filed Dec. 2, 2003 entitled “Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers,” typically start with a first semiconductor layer having a first orientation directly bonded to a second semiconductor layer having a second orientation different from the first. Selected areas of the first semiconductor layer are amorphized by ion implantation, and then recrystallized into the orientation of the second semiconductor layer using the second semiconductor layer as a crystal template.
FIGS. 1A-1D show a “top amorphization/bottom templating” version of the ATR method of U.S. patent application Ser. No. 10/725,850 for forming a bulk hybrid orientation Si substrate. In this version of ATR, the first semiconductor layer being amorphized is on the top and the second semiconductor layer acting as a template is on the bottom. Specifically, FIG. 1A shows the starting substrate 10 which comprises a top silicon layer 20 having a first crystal orientation, a bottom silicon layer or substrate 30 having a second crystal orientation different from the first, and a bonded interface 40 between them. FIG. 1B shows the substrate of FIG. 1A (designated now as 10′) after formation of dielectric-filled shallow trench isolation (STI) regions 50. Selected regions of top Si layer 20 are then subjected to amorphizing ion implant 60 to produce one or more amorphized regions 70, as shown in FIG. 1C. The amorphizing ion implant 60 would typically be performed with Si or Ge ions. Amorphized regions 70 span the entire thickness of the upper Si layer 20, and extend into the lower Si layer 30. The amorphized regions 70 are then recrystallized into the second crystal orientation, using the lower Si layer 30 as a template, to produce (idealized) planar hybrid orientation substrate 80 with recrystallized, changed-orientation Si region 90. In this example, the orientations of Si regions 30 and 90 may have a (100) orientation, while the Si regions 20 may have a (110) orientation.
In contrast to the idealized outcome shown in FIG. 1D, recrystallization of the amorphized Si region 70 in the structures of FIG. 1C would typically result in the structure of FIG. 2A, with end-of-range defects 97 and corner defects 99. End-of-range defects are well studied and have been reported in, for example, J. P. de Souza and D. K. Sadana, in Handbook on Semiconductors: Materials, Properties and Preparation, edited by S. Mahajan (North Holland, 1994), Vol. 3b, p. 2033, and corner defects have been described previously by N. Burbure and K. S. Jones in “The effect of oxide trenches on defect formation and evolution in ion-implanted silicon,” Mat. Res. Soc. Symp. Proc. 810 C4.19 (2004). As described in U.S. patent application Ser. No. 11/031,142, end-of-range defects 97 remaining after ATR may be eliminated by including a high temperature (approximately 1300° C.) anneal as part of the recrystallization process, as shown in FIG. 2B. However, this high temperature annealing is not expected to be effective in eliminating corner defects 99. While more aggressive annealing (e.g., more than a few hours at temperatures higher than 1300° C.) might help to a limited degree, it is not a preferred option due to concerns about reaction and dissolution of oxide layers contained in the STI fill.
FIGS. 3A-3E show the geometry of corner defects 99 in relation to a FET device that might comprise ATR'd region 90. Specifically, FIGS. 3A-3B show top views of ATR'd region 90 with (FIG. 3B) and without (FIG. 3A) FET 112 including a gate and a gate dielectric. Reference numeral 50 denotes the dielectric filled trench region. FIGS. 3C-3E show cross section views of FIG. 3B through lines C-C1, D-D1, and E-E1, respectively. Corner defects 99 are a particular concern in circled regions 118, where they are directly under the gate and the gate dielectric of FET 112 and may contribute to undesirable leakage.
One could devise methods to repair corner defects 99, but none appear to be very practical. For example, one could re-amorphize the ATR'd regions to a shallower depth than the initial amorphization, and then recrystallize. This would still leave corner defects, but they would be smaller, since the corner defect size scales with the amorphization depth, as discussed in the publication by Burbure and Jones mentioned above. Alternatively one could remove the corner defect regions and replace them with an insulator or epitaxially-grown Si. However, the steps to do this are quite involved. It is therefore clear that the preferred approach would be to avoid forming corner defects in the first place.
Corner defect formation can be avoided with the the ATR-before-STI process flow of FIGS. 4A-E. Specifically, FIG. 4A shows a starting substrate 10 such as shown in FIG. 1A. FIG. 4B shows the substrate 10 of FIG. 4A being subjected to amorphizing ion implant 60 to produce one or more amorphized regions 120 and non-amorphized regions 20′. Amorphized regions 120 span the entire thickness of the upper Si layer 20, and extend into the lower Si layer 30. Amorphized regions 120 are then recrystallized using the lower Si layer 30 as a template to produce changed-orientation Si region 130 bordered below by end-of-range defects 97 and bordered laterally by potentially defective edge regions 140, as shown in FIG. 4C. End-of range defects 97 are then removed by a high temperature defect-removal anneal leaving annealed edge regions 140′, as shown in FIG. 4D. Annealed edge regions 140′ are then replaced by STI regions 150, as shown in FIG. 4E.
FIGS. 5A-5D, which are provided by the applicants of the present application, show cross-section SEM images of border regions corresponding to 140 in FIG. 4C for the case of a 200-nm-thick 110-oriented Si DSB (direct silicon bonded) layer on a 100-oriented Si handle wafer. All samples were first coated with Cr, cleaved, and then subjected to a short Secco etch to highlight interfaces and defects. The Secco etch includes a mixture of HF, K2CrO7, and H2O. FIG. 5A shows a sample after a patterned amorphization with 4E15/cm2 220 keV Ge at a substrate temperature of 10° C., prior to recrystallization annealing. Amorphized region 155 is bordered below by 100-oriented substrate 157 and bordered laterally by non-amorphized 110-oriented DSB region 159. Bonded interface 161 is between Si substrate 157 and a DSB region 159. Non-amorphized DSB regions comprise 5 μm squares (aligned with the 110 directions of the 100-oriented substrate) on approximately 10 μm centers. FIGS. 5B-5C show the sample of FIG. 5A after a 900° C./1 minute rapid thermal recrystallization anneal along two perpendicular cleaves coinciding with the 110 directions of the 100-oriented substrate, one along the 100 direction of the DSB layer and the other perpendicular to it. Region 163 has recrystallized into the 100 orientation of the substrate, separated from the 110-oriented regions by angled interfaces 165 and/or 167.
The images of FIGS. 5B-5C make it clear that the orientation-changing ATR methods taught in U.S. patent application Ser. No. 10/725,850 can provide structures including Si regions of different orientations laterally separated by characteristically angled border regions. The form and defectivity of these border regions depends on the kinetics of the various growth fronts as well as the initial orientation of the crystal planes from which the recrystallization is templated; for example, defective region 171 is present in the image of FIG. 5B, but not the image of FIG. 5C. In view of the possibility that these characteristically angled border regions will have uses not anticipated or described in the prior art, it is therefore asserted that the hybrid orientation ATR methods taught by U.S. patent application Ser. No. 10/725,850 may be employed to create Si regions with these characteristically distinctive borders, without departing from the scope of the original inventive method.
While solving the corner defect problem, the ATR-before-STI approach of FIGS. 4A-4E unfortunately gives rise to another problem: when the recrystallization and high temperature defect-removal anneals are performed before STI formation, the non-ATR'd Si regions (or islands) 20′ can “disappear” by converting to the orientation of the underlying substrate. FIG. 5D shows a cross section analogous to the one of FIG. 5C at early stages of this disappearance/conversion process (i.e., after a slow furnace ramp to 1250° C.). The image suggests that (at least for the case of the 110-oriented islands embedded in a 100-oriented substrate) disappearance of non-ATR'd regions proceeds by a gradual bottom corner rounding or erosion rather than by a lateral translation of the edge regions. Interestingly, the stability of non-ATR'd 110-oriented Si islands embedded in 100-oriented Si substrates appears to be a concern only when the edges of 110-oriented islands such as 20′ in FIG. 4 are bordered by changed-orientation Si regions 130, since the 110-oriented islands 20′ bounded by oxide-filled trenches survive the high temperature defect-removal anneals with their original orientation intact.
Another concern with the ATR methods of U.S. patent application Ser. No. 10/725,850 is their reliance on ion implantation amorphization as the means by which the initial orientation information is removed from regions selected for orientation change. Alternative methods for effecting such crystalline-to-noncrystalline transformations in these selected regions would also be highly desirable.